In case of highly accurately measuring a direct-current voltage or a direct current of a device under test (DUT) by a semiconductor testing apparatus, each accurate component is required in an operational amplifier, a peripheral resistance, an AD converter and others.
When mounting these circuits on a silicon substrate, there is a problem that a manufacturing process of the silicon substrate becomes complicated, laser trimming is required or a chip size is increased in order to realize highly accurate measurement.
FIG. 1 is a circuit configuration view of a primary part of one channel, showing a voltage source and current measurement (VSIM) which applies a desired voltage to a DUT and measures a current flowing at this moment. This measures a quantity of a current which breaks in an IC pin of the DUT through pin electronics of a test head and flows through the IC pin.
As well known, in a VSIM for a high voltage, a voltage up to, e.g., approximately ±40 V is applied to a DUT, and a current measurement range is switched in order to measure a current quantity in a wide dynamic range of pico-ampere/micro-ampere/mill-ampere. In a VSIM for a low voltage, a voltage up to, e.g., approximately ±10 V is applied to a DUT, and a current measurement range is switched in order to measure a current quantity of micro-ampere/milli-ampere. It is to be noted that a semiconductor testing apparatus include a predetermined number of these VSIMs. Here, since the semiconductor testing apparatus and the voltage source and current measurement (VSIM) are publicly and technically known, any other signals or constituent elements and their detailed explanation will be eliminated except the primary part according to the present invention.
As shown in FIG. 1(a), as simple primary constituent elements of a VSIM, there are included a DA converter 10, an operational amplifier A1, a current detection resisting means RM and a current measuring portion 100.
The DA converter 10 generates a positive/negative set voltage 10s which should be applied to an IC pin of a DUT. For example, it generates an arbitrary voltage which is not less than ±40 V.
The operational amplifier A1 is an operational amplifier for error reduction and power increase which receives the set voltage 10s and supplies it as a test voltage VS to the IC pin of the DUT through the current detection resisting means RM.
The current detection resisting means RM is inserted in series into a line connected with the IC pin of the DUT, and a resistance value with which a quantity of a current flowing through this line is converted into a potential difference Vx of approximately several-hundred milli-volt is used. A common mode voltage Va and a detection voltage Vb which are generated at each of both ends of the current detection resisting means RM are supplied to the current measuring portion 100. In this example, as to the current detection resisting means RM, there are a case in which the current detection resisting means RM is constituted by using a single resistance alone and a case in which a current measurement range function formed of a plurality of resistances and a switching relay is included as shown in FIG. 1(c) because of a measurement range or any other reason.
The current measuring portion 100 receives the common mode voltage. Va and the detection voltage Vb at the both ends of the current detection resisting means RM, performs quantization conversion, obtains a result as measurement data of a potential difference Vx between these voltages, and specifies a quantity of the current flowing through the IC pin of the DUT based on this data.
FIG. 1(b) is a first internal fundamental circuit diagram of the current measuring portion. This is an example in which operational amplifiers A2 and A3, resistances R1, R2, R3 and R4, a changeover switch SW1 and an AD converter 20 are provided as constituent elements.
A structure of the operational amplifier A3 and the resistances R1, R2, R3 and R4 is a general differential amplification structure which receives two signals, converts them into a differential signal Vc corresponding to a potential difference Vx between these signals, and outputs the obtained signal. The operational amplifier A2 is just a voltage buffer. In this example, when performing accurate measurement, a voltage division ratio of the resistances R1 and R2 and a voltage division ratio of the resistances R3 and R4 must precisely match with each other.
The changeover switch SW1 is a switching relay which is used when a connection is switched to a circuit earth side and 0 V as a reference is measured in order to specify an offset voltage or the like of the operational amplifiers A2 and A3.
The AD converter 20 receives a differential signal Vc from the operational amplifier A3, and outputs measurement data obtained by quantization conversion of the received signal.
Error factors involved by the common mode voltage and the voltage division resistances will now be evaluated by using numerical expressions. Here, α is an error rate with respect to a target resistance value, and n is a gain (an amplification degree).
Error factors of the respective resistances can be regarded as R1=R(1+α), R2=n*R(1−α), R3=R(1−α), and R4=n*R(1+α).
An offset=Ao is assumed as an error factor of the operational amplifier A2, and an offset=Bo is assumed as an error factor of the operational amplifier A3.
The differential signal Vc to be outputted can be represented by an expression Vc=Va*(R4/(R3+R4))*((R1+R2)/R1)−Vb*(R2/R1)−Ao*(R2/R1)+Bo*((R1+R2)/R1).
In this example, when Vb=Va+Vx is substituted, there can be obtained an expression Vc=Va*[(R4/(R3+R4))*((R1+R2)/R1)−(R2/R1)]−Vx*(R2/R1)−Ao*(R2/R1)+Bo*(R2/R1+1).
A common mode voltage error n1 can be represented by an expression n1=[(R4/(R3+R4))*(R1+R2)/R1]−(R2/R1)].
A gain error n2 can be represented by an expression n2=(R2/R1).
An offset error n3 can be represented by an expression n3=Ao*(R2/R1)+Bo*((R1+R2)/R1).
When the common voltage error n1 is calculated based on the above-described expressions, there can be obtained an expression n1={n(1+α)/[(1−α)+n((1+α))]*{[(1+α)+n((1−α))/(1+α)]−[n(1−α)/(1+α].
Here, when 1−α=A and 1+α=B are substituted, there can be obtained an expression n1=(B+nA)/(A+nB)−A/B=(A*A−B*B)/(AB−nB*B)=[1−2α+α*α−(1+2α+α*α)]/[1−α*α+n(1+2α+α*α)].
Here, since α<<1 is achieved and α*α and 2αn are sufficiently smaller than 1 so that they can be approximated by 0,
there can be generated a common mode voltage error represented as n1′=−4α/(1+n+2αn)≈4α/(1+n). For example, when numerical values of a common mode voltage Va=10 V, a resistance error α=0.1% and a gain n=1 are substituted, the common mode voltage error takes a value of 10 V*(4*0.1%)/2=20 mV. There is a problem that this error value results in a serious measurement error factor.
On the other hand, the resistance has peculiar non-linear characteristics of a resistance element called a voltage coefficient. In the peculiar non-linear characteristics, a resistance value varies depending on a voltage which is applied to the resistance as shown in an explanatory view of FIG. 10 in which a non-linear deviation is generated with respect to an ideal resistance due to an applied voltage.
For example, although a highly accurate resistance using a nickel-chrome-based thin film or the like has a small voltage coefficient, a polysilicon-based resistance formed in an monolithic IC may have a voltage coefficient which varies 0.1 to 0.5% with 1 V in some cases.
Therefore, since the resistances R1 to R4 for voltage division complicatedly vary due to the common mode voltage Va as well as the potential difference Vx of Va−Vb in the above-described circuit, there is a problem that resistances with good characteristics which are formed of nickel chrome or the like are required. On the contrary, when a voltage to be applied to the resistances is in proportion to the differential signal Vc as a measurement value, the peculiar non-linear characteristics of the resistance elements can be corrected by calibration or the like.
FIG. 2(b) is a second internal fundamental circuit diagram of the current measuring portion 102, which is a primary fundamental structure of the current measuring portion which measures a current of the IC pin of the DUT in each of a plurality of channels disclosed in Japanese Patent Application Laid-open No. 174113-1999 (a voltage source and current measuring circuit of an IC tester). Here, FIG. 2(a) shows a primary fundamental structural example when a current flowing through the IC pin of one channel is measured. This is a technique which directly AD-converts each of the common mode voltage Va and the detection voltage Vb at both ends, stores them in a data memory, and then calculates a potential difference Vx by software processing. According to this technique, since the resistances R1 to R4 for voltage division are not used, the problem of the common mode voltage error is solved.
However, there is adversely a problem that an AD converter having a high-input voltage range and a high resolution is required for-the AD converter 45. For example, in cases where measurement is carried out with a resolution of ±0.1% (±1000) when the potential difference Vx is 1 Vmax, a 11-bit resolution (±1000) can suffice if a test voltage VS is 1 V. However, there is a problem that an AD converter having a high-input voltage range with a 15-bit resolution (±10000) is required if the test voltage VS is 10 V and an AD converter having a high-input voltage range with an 18-bit resolution (±100000) is required if the test voltage VS is 100 V. There is a drawback that an AD converter which can cope with a high-input voltage range and a high resolution is expensive.
As described above, in the current measuring portion according to the prior art, as shown in FIG. 2, the common mode voltage Va and the detection voltage Vb at the both ends of the current detection resisting means RM are directly subjected to quantization conversion by the AD converter, and hence there is a problem that an AD converter having a high-input voltage range and a high resolution is required. An AD converter which can cope with a high-input voltage range is expensive. The semiconductor testing apparatus must include such AD converters for several-ten channels, which results in a problem that the testing apparatus becomes expensive.
It is, therefore, an object of the present invention to provide a semiconductor testing apparatus comprising a current measuring portion which converts a load current quantity at the time of application of a relatively-high test voltage to fall within a low-voltage range and then subjects the low-voltage range to quantization conversion with a predetermined measurement resolution even when the relatively high test voltage is applied to a DUT.
Further, it is another object of the present invention to provide a semiconductor testing apparatus comprising a voltage source and current measurement (VSIM) having a current measuring portion which can convert a load current quantity at the time of application of a relatively high test voltage to fall within a relatively low voltage range and then subject the relatively low voltage range to quantization conversion with a predetermined measurement resolution even when the relatively high test voltage is applied to a DUT.
Furthermore, it is still another object of the present invention is to provide a semiconductor testing apparatus comprising a current measuring portion having a circuit configuration which can minimize an impact on a measurement accuracy even if there are irregularities in resistances formed on an IC when forming the current measuring portion as a monolithic IC.
Moreover, it is yet another object of the present invention to provide a semiconductor testing apparatus comprising a current measuring portion having a circuit configuration which can minimize an impact on a measurement accuracy by performing linear correction processing even if peculiar non-linear characteristics of resistance elements formed on an IC exist when forming the current measuring portion as a monolithic IC.